A Delayed Buffered Technique Using The Concept Of Gated Driven Tree For Optimizing The Power

This Project presents circuit design of a low-power delay buffer. In order to store a data in a memory, the buffers in the memory should be selected sequentially. For selecting buffers, ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half. The C-element gated-clock strategy is proposed to reduce the power consumption. The gated-driver-tree idea is also employed in the input and output ports of the memory block to decrease their loading, thus saving even more power. Introduction The skyrocketing increasing transistor count and circuit density of modern very large scale integrated (VLSI) circuits have made them extremely difficult and expensive to test comprehensively. The DFT method in a digital processing chip of mobile communications, the delay buffer takes up a large portion of the circuit layout. If the power consumption of the delay buffer could be reduced significantly, the overall power consumption of the digital processing chip could be reduced significantly as well. On the other hand, as these chips are working at even higher operation frequencies, a new, low-power delay buffer should be operable under high frequencies. Fig.1 is a schematic diagram showing a conventional delay buffer having a length N and data width W bits using shift registers. As illustrated, the delay buffer contains N times W shift registers, arranged between the input and the output in N stages, each with W shift registers. The N times W shift registers are triggered by a same clock signal CLK. For every clock period of CLK, W-bit data is shifted from W shift registers of a previous stage to those of a next stage, and so on. A W-bit data input N clock periods ago therefore would be delayed and output after N clock periods. The clock signal CLK is provided to all N times W shift registers, contributing to the high power consumption. Moreover, the N times W shift registers would also take up a large die area. In general therefore, in real life, delay buffer such as the one in Fig.1 is most commonly used. Fig.1: Dual-port SRAM memory One of the common delay buffer implementation is a dual-port SRAM memory whose operation is different from that of the shift-register-based delay buffer. For an N times W SRAM-based delay buffer, there is no data movement between stages. Instead, at every clock period, a W-bit data is written to one of the N times W storage locations of the SRAMbased delay buffer, and another W-bit data that is written N clock periods ago is output. The power consumption of a SRAM-based delay buffer is mainly from the address decoder and the drivers for its input and output ports. As memory related technology has already quite mature and satisfactory results in terms of layout area and speed are achievable. Therefore in reality a delay buffer is often implemented using SRAM memory. Characteristics Terms For Various Memory Devices The following terms are most commonly used for identifying comparative behaviour of various memory devices and technologies. Storage Capacity It is a representative of the size of the memory. The capacity of internal memory and main memory can be expressed in terms of number of words or bytes. The storage capacity of external memory is normally measured in terms of bytes. Unit of transfer Unit of transfer is defined as the number of bits read in or out of the memory in a single read or write operation, for main memory and internal memory; the normal unit of transfer of information is equal to the word length of a processor. In fact it depends on number of data lines in and out of the memory module. In general, these lines are kept equal to the word size of the processor. The unit of transfer of external memory is normally quite large and is referred to as block of data. Access Modes Once we have defined the unit of transfer next important characteristics is the access mode in which the information is accessed from the memory. A memory is considered to consist of various memory locations. The Rajya Lakshmi G, Radha Krishna T, Lowkya Ch, Basheer Ali Sheik, P Mahesh, L Srikanth / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 2,Mar-Apr 2012, pp.727-733 728 | P a g e information from memory devices can be accessed in the following ways: a) Random Access Memory (RAM) It is the mode in which any memory location can be accessed in any order in the same amount of time. Ferrite and Semiconductor memories which generally constitute main memory are of this nature. The storage locations can he accessed independently and there exist separate access mechanism for each location. b) Sequential access On the other hand we have memories which can be accessed in pre-defined sequences for example; the songs stored on a cassette can be accessed only one by one. The example of sequential access memory is Magnetic Tape. Here the access mechanisms need to be shared among different locations. Thus, either the location or the read/write head or both should be moved to access the desired location. c) Direct Access In certain cases the information is neither accessed randomly nor in sequence but something in between. In this kind of access, a separate read/write head exist for a track and on a track the information can be accessed serially. These semi-random modes of operation exist in magnetic disks. d) Access Time The access time is the time required between the requests made for a read or write operation till the time the data is made available or written at the requested location. Normally it is measured for read operation. The access time depends on the physical characteristics and access mode used for that device. Permanence or Storage: It is Possible to lose information by the memories over a period of time. The reasons of the loss of information. There are several reasons for information destruction, these are destructive readout, dynamic storage, volatility and hardware failure. If for a particular memory the reading process destroys the stored information. Call it Destructive readout. In such memories the information has to be written back on the same location from which it had been read after each read operation. The reading process where the data is not destroyed on reading is referred to as Non-destructive readout. Background Work & Proposed System Delay buffer works quite similarly like a fixed jitter buffer, that is it will delay the frame retrieval by some interval so that caller will get continuous frame from the buffer. This can be useful when the operations are not evenly interleaved, for example when caller performs burst of put () operations and then followed by burst of operations. With using this delay buffer, the buffer will put the burst frames into a buffer so that get () operations will always get a frame from the buffer (assuming that the number of get () and put () are matched). The buffer is adaptive, that is it continuously learns the optimal delay to be applied to the audio flow at run-time. Once the optimal delay has been learned, the delay buffer will apply this delay to the audio flow, expanding or shrinking the audio samples as necessary when the actual audio samples in the buffer are too low or too high.